1. Field of the Invention
The present invention is directed to devices and methods for generating phase-coherent frequencies.
2. Discussion of the Background
Useful synthesizers are able to generate a large number of frequencies and can switch rapidly between frequencies. Owing to their low cost, ease of control, high switching speed, and ability to generate millions of frequencies, direct digital synthesizers (DDSs) are increasingly popular. DDS integrated circuits (ICs) are available which can generate signals up to approximately 40 MHz with a resolution of less than 0.1 Hz. Unfortunately, the standard DDS method is inherently non-phase coherent.
For a synthesizer to be phase coherent, each instance of a particular frequency must be in phase with every previous instance of that same frequency. In other words, if the synthesizer switches from a frequency .function..sub.A to a frequency .function..sub.B, and then back to .function..sub.A, the second occurrence of .function..sub.A would have the same phase that the first signal would have had if it had not been interrupted. Phase coherence is required in devices, for example, which simulate scanning radars. FIG. 1 illustrates the phases for .function..sub.A and .function..sub.B when switching from .function..sub.A to .function..sub.B and back to .function..sub.A in a non-phase-coherent DDS, and FIG. 2 illustrates the same switching in a phase-coherent DDS.
A typical DDS circuit, as shown in FIG. 3, comprises a P-bit phase step register 1, a phase accumulator 2, and a read-only memory (ROM) 3 containing a sine lookup table. In addition, an external digital-to-analog converter (DAC) (not shown) and a low-pass filter (LPF) (not shown) are added for generating sinusoidal signals. See, e.g., Vadim Manassewitsch, Frequency Synthesizers, Theory and Design (New York: John Wiley & Sons, 1987), pp. 37-43. The components which are most important for this discussion are the phase step register 1 and the phase accumulator 2. The phase accumulator 2 can simply be a digital adder circuit, the output of which is fed back to the input and added to the contents of the phase step register 1.
With each cycle of the system clock, the phase accumulator's 2 output advances by the contents of the phase step register 1. The sine lookup table contained in the ROM 3 converts the digital representation of phase to a digital representation of the amplitude of a sine wave. This digital signal is converted to an analog one by the DAC, and discontinuities in the waveform output are filtered by the LPF.
Since frequency is the rate of change of phase, the frequency generated is ##EQU1## where .function..sub.out is the DDS output frequency, .DELTA..PHI. is phase step of the DDS accumulator, and T.sub.sys is the system clock period. To change frequencies, it is only necessary to change the contents of the phase step register. When a frequency change occurs, the phase of the new frequency is one phase step greater than the old. Thus, the standard DDS circuit is inherently phase continuous, which precludes obtaining the desired phase-coherent behavior.
A known method for coherent DDS is shown in FIG. 4. A DDS circuit can be made phase coherent if, after each frequency change, the phase accumulator is reset to zero on the rising edge of a reset clock, which has a frequency ##EQU2## where .function..sub.sys =1/T.sub.sys and N is the integer divisor associated with the divide-by-N circuit 4 in FIG. 4. The frequency of the output of the DDS 5 is set to be an integer multiple of the reset clock, EQU .function..sub.out =n.times..function..sub.r, (3),
where n is an integer. All frequencies are thus tied to the reset clock, and each rising edge of the reset clock corresponds to a zero-phase point of the output. The DDS 5 in FIG. 4 includes elements 1, 2, and 3, as configured in FIG. 3.
The problem with the scheme shown in FIG. 4 and described above is that it is impossible to simultaneously obtain low dwell time (i.e., the duration between the start of two valid signals at different frequencies) and good frequency resolution. The correct frequency and phase are achieved only after the rising edge of the reset clock. This means that the minimum frequency dwell time is one reset clock period, T.sub.r. However, because the frequency must be an integer multiple of the reset clock, the frequency resolution is 1/T.sub.r. Note that the divide-by-N unit 4 permits improvement of the frequency resolution at the expense of increased dwell time.